Agent Skills

Each Skill is a highly detailed instruction template that guides an AI Agent to generate digital IC design code following industry best practices, covering RTL design, timing constraints, and verification. Generic Skills may not fully meet specific design requirements — customize and refine them for your project to achieve the best results.

🔧

Verilog Module Generator

Intermediate

Generate complete, synthesizable Verilog/SystemVerilog modules from natural language specifications. Encodes latch-free patterns, correct reset strategy, blocking vs non-blocking rules, and signal naming conventions.

RTL Design

🔧

FSM Generator

Intermediate

Generate finite state machines in 1/2/3-block architectures, Moore or Mealy. Includes state encoding strategy (binary/Gray/one-hot), unreachable state recovery, and glitch-free output generation.

RTL Design

🔧

FIFO Generator

Advanced

Generate synchronous or asynchronous FIFOs with proper empty/full detection, Gray-coded CDC pointers, almost-full/empty flags, and AXI-Stream interfaces. Includes depth calculation methodology.

RTL Design

🔧

CDC Synchronizer

Advanced

Generate clock domain crossing circuits: 2-stage synchronizers, pulse synchronizers, handshake-based multi-bit transfer, DMUX synchronizers. Includes MTBF analysis and synthesis attributes to prevent optimization.

RTL Design

⏱️

SDC Writer

Intermediate

Generate complete SDC timing constraint files from design specifications. Covers clock definitions, generated clocks, I/O delays, clock groups, false paths, multi-cycle paths, and operating conditions.

Timing Constraints

✅

Testbench Generator

Intermediate

Generate self-checking Verilog/SystemVerilog testbenches with clock/reset generation, constrained-random stimulus, expected-value checking, pass/fail reporting, and VCD waveform dumping.

Verification

✅

SVA Assertion Writer

Advanced

Generate SystemVerilog Assertions for interface protocol checks, data integrity, FSM correctness, FIFO properties, arbitration, and reset behavior. Includes cover properties for coverage.

Verification

✅

RTL Code Reviewer

Advanced

Perform comprehensive RTL code review against industry standards. Checks for synthesis-simulation mismatches, latch inference, CDC issues, coding style, DFT readiness. Produces categorized report with fix recommendations.

Verification