SDC Constraint File Guide: From Basics to Practice

What is SDC?

SDC (Synopsys Design Constraints) is the industry-standard format for describing timing constraints in chip design. It defines clock frequencies, I/O timing, timing exceptions, and more — critical input for synthesis and place & route.

1. Clock Definition

Primary Clock

create_clock -name clk -period 10 -waveform {0 5} [get_ports clk]

• -name: Clock name
• -period: Clock period (default unit: ns)
• -waveform: Rising and falling edge times

Generated Clock

create_generated_clock -name clk_div2 -source [get_ports clk] \
  -divide_by 2 [get_pins div2_reg/Q]

2. Clock Uncertainty

set_clock_uncertainty -setup 0.1 [get_clocks clk]
set_clock_uncertainty -hold 0.05 [get_clocks clk]

3. I/O Delays

set_input_delay -clock clk 2.0 [get_ports data_in]
set_output_delay -clock clk 2.5 [get_ports data_out]

4. Clock Groups & False Paths

# Physically exclusive clock groups
set_clock_groups -physically_exclusive \
  [get_clocks clk1] [get_clocks clk2]

# False paths
set_false_path -from [get_ports rst_n] -to [get_ports data_out]

5. Practical Tips

1. Top-down approach: Define top-level clocks first, then refine I/O constraints
2. Conservative start: Begin with conservative constraints, tighten before tapeout
3. Align with back-end: Coordinate input/output delay values with the back-end team
4. Use tool checks: Run check_timing to verify constraint completeness

Try the ICHDL SDC Constraint Generator to generate SDC templates online.