Agent Skills
每个 Skill 是一套高度精细的指令模板，指导 AI Agent 按照业界最佳实践生成数字IC设计代码，覆盖 RTL 设计、时序约束和验证三大领域。通用 Skill 可能无法完全满足特定设计需求，建议根据实际项目进行完善和修改后使用，以获得最佳效果。
Verilog Module Generator
Generate complete, synthesizable Verilog/SystemVerilog modules from natural language specifications. Encodes latch-free patterns, correct reset strategy, blocking vs non-blocking rules, and signal naming conventions.
RTL 设计FSM Generator
Generate finite state machines in 1/2/3-block architectures, Moore or Mealy. Includes state encoding strategy (binary/Gray/one-hot), unreachable state recovery, and glitch-free output generation.
RTL 设计FIFO Generator
Generate synchronous or asynchronous FIFOs with proper empty/full detection, Gray-coded CDC pointers, almost-full/empty flags, and AXI-Stream interfaces. Includes depth calculation methodology.
RTL 设计CDC Synchronizer
Generate clock domain crossing circuits: 2-stage synchronizers, pulse synchronizers, handshake-based multi-bit transfer, DMUX synchronizers. Includes MTBF analysis and synthesis attributes to prevent optimization.
RTL 设计SDC Writer
Generate complete SDC timing constraint files from design specifications. Covers clock definitions, generated clocks, I/O delays, clock groups, false paths, multi-cycle paths, and operating conditions.
时序约束Testbench Generator
Generate self-checking Verilog/SystemVerilog testbenches with clock/reset generation, constrained-random stimulus, expected-value checking, pass/fail reporting, and VCD waveform dumping.
验证SVA Assertion Writer
Generate SystemVerilog Assertions for interface protocol checks, data integrity, FSM correctness, FIFO properties, arbitration, and reset behavior. Includes cover properties for coverage.
验证RTL Code Reviewer
Perform comprehensive RTL code review against industry standards. Checks for synthesis-simulation mismatches, latch inference, CDC issues, coding style, DFT readiness. Produces categorized report with fix recommendations.
验证